The present invention relates to a programmable frequency divider, and more particularly to a full binary programmed frequency divider which uses a dual modulus prescaler, where neither modulus of the prescaler is a power of 2.
A programmable frequency divider is a circuit which divides down an input signal to provide an output pulse train where the repetition frequency of the output pulse train is a selected fraction of the frequency of the input signal. The repetition frequency of the output pulse train can be varied by changing the division ratio which is set into the frequency divider.
Frequency dividers of this type are commonly employed in frequency control of frequency synthesizers. With the application of frequency synthesis techniques to high frequency communications applications, a need has arisen for a high speed, fully programmable frequency divider. Available dividers which are fully programmable, however, do not meet speed requirements, whereas those dividers that are fast enough lack programming capacity.
The lack of availability of frequency dividers having the required characteristics has led to the development of "pulse swallowing" dividers. Programmable frequency dividers of this general type are described in the article entitled "Making Programmable UHF Counters When None Are Available Or . . . Pulse Swallowing Revisited"; this article appeared in volume 3, No. 4 of the Fairchild Journal of Semiconductor Progress. These dividers combine dividers that are very fast, but which lack programming capacity, with dividers that are fully programmable, but rather slow, to produce a resulting divider which appears to be very fast, but yet is fully programmable. The "fast" dividers used in these techniques are conventional dual modulus prescalers which divide the input signal by a selected one of two moduli. Off-the-shelf prescalers have moduli of 10 and 11, and 5 and 6, with the (divide by 10/11) prescaler being most commonly used.
Programmable pulse swallowing dividers are conventionally constructed to accept binary-coded-decimal (BCD) programming signals. This leads to somewhat awkward programming, and inefficient use of the programming lines. A more efficient use could be made of the programming lines and capabilities of the system if a pulse swallowing divider could be implemented employing full binary programming.